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Multi-lag cross-correlations (X-Corr) are essential building blocks in radar and communication for range/velocity detection and synchronization. Performing X-corrs necessitates efficient delay and correlation blocks. Traditionally, high bandwidth X-corr is performed using high-speed ADCs followed by digital multiply-and-accumulates (MACs). However, 5–20 TOPS/W X-Corr efficiencies lead to 0.1-1W per cross-correlator, limiting deployability in power-constrained applications. Alternatively, to realize X-corr using prior single-lag analog correlators, wideband analog delays (>10ns delays with 4GHz BW) should be integrated on chip to enable multiple lags. Furthermore, replicating N analog correlators, leads to an impractical chip area. Therefore, practical analog X-Corr requires: (i) high input bandwidths, (ii) long correlation length, N for high signal processing gain (SPG=10log10(N)), (iii) high compute-efficiency (>100 TOPS/W) with compute accuracy compared to digital MACs (>7-bit), (iv) single-shot readout across all N X-corr lags in a compact area. In this work, we leverage a sampling-based approach to create large analog delays and area/power-efficient four-transistor analog compute cell to present a margin-propagation (MP) based fully-analog X-Corr compute engine in 22nm SOI-CMOS achieving: (i) 1-4GS/s input, (ii) single-shot 256-length X-Corrs across all 256 lags resulting in a 256x256 X-correlator, 8.2-8.5 bit compute accuracy or hardware dynamic range (HDR) of 51-53dB, (iii) high compute efficiency of 996–1060 TOPS/W (6.6x better than SoA), (iv) high compute density of 1.3 TOPS/mm2 (7x better than SoA). We also demonstrate an X-band code-domain radar with a range resolution of 15cm across 256 range bins, supporting up to 1024 chirp averages with a 115Hz refresh rate. 

| The relentless demand for data in our society has driven the continuous evolution of wireless technologies to enhance network capacity. While current deployments of 5G have made strides in this direction using massive multiple-input–multiple-output (MIMO) and millimeter-wave (mmWave) bands, all existing wireless systems operate in a half-duplex (HD) mode. Full-duplex (FD) wireless communication, on the other hand, enables simultaneous transmission and reception (STAR) of signals at the same frequency, offering advantages such as enhanced spectrum efficiency, improved data rates, and reduced latency. This article presents a comprehensive review of FD wireless systems, with a focus on hardware design, implementation, cross-layered considerations, and applications. The major bottleneck in achieving FD communication is the presence of self-interference (SI) signals from the transmitter (TX) to the receiver, and achieving SI cancellation (SIC) with real-time adaption is critical for FD deployment. The review starts by establishing a system-level understanding of FD wireless systems, followed by a review of the architectures of antenna interfaces and integrated RF and baseband (BB) SI cancellers, which show promise in enabling low-cost, small-form-factor, portable FD systems. We then discuss digital cancellation techniques, including digital signal processing (DSP)- and learning-based algorithms. The challenges presented by FD phased-array and MIMO systems are discussed, followed by system-level aspects, including optimization algorithms, opportunities in the higher layers of the networking protocol stack, and testbed integration. Finally, the relevance of FD systems in applications such as next-generation (xG 

The self-interference (SI) channels in full-duplex (FD) radios have large nano-second-scale delay spreads, which poses a significant challenge in designing SI cancelers that can emulate the SI channel over wide bandwidths. Passive implementations of high delay lines have a prohibitively large form factor and loss when implemented on silicon, whereas active implementations suffer from noise and linearity penalties. In this work, we leverage time-interleaved multi-path switched-capacitor (SC) circuits to provide large wideband delays with a small form factor and low power (LP) consumption to implement RF and baseband (BB) cancelers in an FD receiver (RX). We utilize capacitor stacking to obtain passive voltage gain to compensate for the loss of these delay elements, thus permitting an increased number of interleaved paths and, hence, a higher delay. Furthermore, to reduce the RX noise figure (NF) penalty due to injecting the cancellation signal into the receiver, we introduce a novel low-noise trans-impedance amplifier (LNTA) architecture, which injects the cancellation signal into RX and also accomplishes finite impulse response (FIR) filter weighting and summation. The FD receiver is implemented in a standard 65-nm CMOS process and operates from 0.1 to 1 GHz. The RF/BB canceler delay cells have real-/complex-valued weighting with delays ranging